This invention relates to an output circuit used in the last stage of a driver circuit or an amplifier circuit of semiconductor components, and more particularly, to an output circuit having the capability of high speed and high current output operation, as well as low power consumption in a steady state. The output circuit of the present invention can be advantageously implemented as a driver in a semiconductor test system for accurately driving the input pins of the semiconductor device under test, however, the present invention can also be effectively applied to an output stage of general purpose electronic circuits.
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system such as an IC tester, a semiconductor device to be tested is provided with test signals (test patterns) formed by IC testers at its appropriate device pins at predetermined test timings. The IC tester then receives the output signals from the device under test produced in response to the test signals. The output signals are sampled by the strobe signals at predetermined timings and then compared with the expected data to determine whether the device under test performs the intended functions correctly.
The test signal waveforms applied to the device under test via driver are precisely controlled their voltage values as well as timings of rising and falling edges depending on the types and test purposes of the particular device under test. Therefore, in order to accurately transmit the test signal waveforms to the device under test, the output circuit must be able to operate at high speed and with large currents. Further, the recent semiconductor devices have input and output pins of several hundreds or more, thus, the semiconductor test system must also have test channels of several hundreds or more. As a result, each output circuit of the driver to have lower power consumption is crucial to the contribution of low power consumption in the test system as a whole.
The output circuit of the present invention is not limited to the application of the above noted semiconductor test system, and thus, can be widely used in the output stage of various electronic circuits and effectively used in, for example, output stages of amplifier circuits. However, for convenience of illustration, the present invention is described below in the case where it is applied to a semiconductor test system.
Such an output circuit of conventional technology is shown in FIG. 1. This is a typical example of a circuit structure requiring current drive capability, such as a driver circuit or an amplifier circuit. In the example of FIG. 1, an output circuit 10 is comprised of an input unit consisting of transistors Q1 and Q2, an output unit consisting of transistors Q3 and Q4, constant current sources for flowing currents I1 and I2, as well as resistors R1, R2, and R3. The output circuit 10 supplies, for example, test signals to a semiconductor device under test with a predetermined current value under a predetermined output impedance.
In such an application in a semiconductor test system for testing a semiconductor device which requires high speed operations, large output current, and low power consumption, it is difficult to satisfy all of such requirements by the conventional circuit structure shown in the drawing. Specific examples of such problems will be explained in the following. Here, it is assumed that the maximum current output supplied to a load, for example, an input pin of the semiconductor device under test, from the output circuit is 70 mA (milliampere) and output impedance of the output circuit is 50 xcexa9(ohms).
Case 1
This is a case where the output circuit is designed to achieve low power consumption as a primary objective. In this case, resistance of resistors R1 and R2 in the last stage are set to zero, i.e., R1=R2=0 xcexa9, currents I3 and I4 in the steady state of the transistors Q3 and Q4 are set to 10 mA, i.e., I3=I4=10 mA, and currents I1 and I2 at the steady state of the transistors Q1 and Q2 are set to 5 mA, i.e., I1=I2=5 mA. In this setting, since a transistor junction of each of the transistors Q3 and Q4 need to be large enough in order to operate at the maximum current output of 70 mA. Thus, the physical size of the transistors Q3 and Q4 must be large.
In this circuit structure, a voltage Vbe between the base and the emitter of the transistor Q1 and a voltage Vbe between the base and the emitter of the transistor Q3 become equal to each other, and a voltage Vbe between the base and the emitter of the transistor Q2 and a voltage Vbe between the base and the emitter of the transistor Q4 also become equal to each other. Further, generally in a transistor, the following relationship is known between emitter (collector) current I, a voltage Vbe between a base and an emitter, and saturation current Is (K is constant):
I=Isxc2x7exp(KVbe)xe2x80x83xe2x80x83(1)
The saturation current Is mentioned here is known to be a function of a physical size of a transistor junction. A transistor which is necessary to flow a large current has a large saturation current Is, resulting in a large physical size. Even when these transistors Q3 and Q4 in the last stage have to flow a large current, these transistors still have a current gain (amplification factor) of several tens or so, making it unnecessary for the input transistors Q1 and Q2 to drive a large current.
However, in order for the voltage Vbe between the base and emitter of the transistor Q1 to be equal to the voltage Vbe between the base and emitter of the transistor Q3 when flowing the current 5 mA, the transistor Q1 must have a saturation current Is which is half of the transistor Q3 under the equation (1). The transistor Q1, therefore, has to be physically large which can operate at 35 mA. The relationship between transistors Q2 and Q4 is the same as that of the transistors Q1 and Q3. As a result, the transistors Q1 and Q2 become large transistors which can operate at 35 mA, although they only need to drive 5 mA. Since transistors having a large physical size typically have large stray capacitance and parasitic capacitance, and therefore are not suitable for high-speed operations.
Case 2
This is a case where the output circuit is designed to achieve a high speed operation as a primary objective. In this case, the resistors R1 and R2 are set to R1=R2=0xcexa9, and the currents I1 and I2 are set to I1=I2=5 mA, and the transistors Q3 and Q4 are to operate at the maximum current of 70 mA like the case 1 above. In the case 2, it is assumed that the transistors Q1 and Q2 are optimized for flowing the current value of 5 mA. In other words, the transistors Q1 and Q2 are formed in the minimum required size sufficient to drive the current value of 5 mA. Thus, the physical size of the transistors Q1 and Q2 can be {fraction (1/7+L )} of the physical size mentioned in the case 1 where the transistors Q1 and Q2 are sized to drive the current value of 35 mA. Since parasitic capacity is smaller and conductive paths are shorter in the transistors Q1 and Q2, a high-speed operation is possible.
Here, the small size of the transistors Q1 and Q2 means that the saturation current Is also small, and thus, a voltage Vbe between the base and emitter has to be larger than that of the case 1 in order to drive the current value of 5 mA. Hence, the voltage Vbe between the base and emitter of each of the transistors Q3 and Q4 becomes large accordingly. As a consequence, a large current will flow through the transistors Q3 and Q4 even when there is no load is provided at the output, which contradicts the reduction of power consumption.
Case 3
This is a case where the output circuit is designed to achieve both the high speed operation and the lower power consumption as a primary objective. In order to achieve the high speed operation and low consumption power, the currents I3 and I4 are set to I3=I4=10 mA, the current I1 and I2 are set to I1=I2=5 mA, and the transistors Q1, Q2, Q3, and Q4 are the same as in the case 2 above. In order to satisfy this relationship, the difference between the voltages Vbe of the transistors Q1 and Q2 and the voltage Vbe of the transistors Q3 and Q4 is offset by voltage drops across the resistors R1 and R2. In other words, the sum of the voltage Vbe between the base and emitter of the transistor Q3 and the voltage across the resistor R1 has to be equal to the voltage Vbe between the base and emitter of the transistor Q1. Similarly, the sum of the voltage Vbe between the base and emitter of the transistor Q4 and the voltage across the resistor R2 has to be equal to the voltage Vbe between the base and emitter of the transistor Q2. In order to satisfy this relationship, resistance value of the resistors R1 and R2 becomes, for example, approximately 6 ohms.
In this case, both high-speed operation and low power consumption can be achieved in the output circuit. However, this configuration has a problem in that the output impedance rapidly increases when the output current value becomes large. As explained above, this circuit assumes that the maximum current of 70 mA can be supplied from the output transistors to the load. When the output current value from one of the output transistors exceeds a certain value, then the other output transistor cannot be sufficiently forward biased because of the voltage drop across the resistance, which causes the other output transistor to turn off.
For example, when this output current value exceeds 30 mA in a positive direction (from the power source V+ to the load via the transistor Q3), the voltage drop caused by the current and the resistor R1 becomes large, lowering the electric potential of the node O in FIG. 1 and turning the transistor Q4 off. Similarly, when the current value exceeds 30 mA in a negative direction (from the load to the power source Vxe2x88x92 via the transistor Q4), the voltage drop caused by the current and the resistor R2 becomes large, increasing the electric potential of the node O and turning the transistor Q3 off.
When both of the transistors Q3 and Q4 are on, the output impedance of the output circuit is equal to a parallel connection of two series circuit (1) and (2) where the series circuit (1) is a series connection of the output resistance of the transistor Q3 and the resistor R1 and the series circuit (2) is a series connection of the output resistance of the transistor Q4 and the resistor R2. However, when one of the transistors is turned off, the output impedance value as a whole becomes only one of the series circuit (1) or (2), and that impedance value, for example, will be twice as much as that when the two transistors are on. Due to this, a precise test signal cannot be supplied to the load, such as a semiconductor device under test.
Therefore, it is an object of the present invention to provide an output circuit which is capable of high-speed operation, large output current generation, as well as low power consumption to be used at an output stage of various electronic circuits.
It is another object of the present invention to provide an output circuit that can be advantageously used in an output stage of a driver circuit of a semiconductor test system in order to supply test signals to semiconductor devices under test.
It is a further object of the present invention to provide an output circuit which is capable of achieving high-speed operation, large current output generation, as well as low power consumption all at the same time, and can be fabricated in a small circuit scale at low cost.
The output circuit of the present invention uses transistors of large current operation only for the last stage transistors, and transistors of small current and high-speed operation for other transistors. The difference in the base-emitter voltage between those different types of transistor is offset by a voltage drop across a resistor network. The output circuit further includes an inverse current circuit for supplying an inverse current to compensate the voltage drop across the resistor network.
Accordingly, the output circuit of the present invention is a circuit for converting the input signal to an output signal of desired current level and supplying the output signal to the load. The output circuit of the present invention is used in an output stage of an electronic circuit. The output circuit includes an input transistor for receiving an input signal, a pair of output transistors for supplying an output signal to the load at a desired current level, a resistor network provided between the output transistors and having a connection point for supplying the output current to the load, a level shift circuit for shifting a bias voltage of the input transistor to determine a bias voltage of the output transistors thereby defining bias current in the output transistors, and an inverse current circuit for supplying a current to the resistor network which is opposite to the current supplied to the resistor network from the output transistor when the output current from one of the output transistors to the load exceeds the predetermined value.
In the embodiment of the present invention, the output circuit includes a constant current source for supplying a constant current to the input transistor and the level shift circuit. Preferably, the pair of output transistors mentioned above are structured in a complementary type circuit where one is an NPN transistor and the other is a PNP transistor. Further, the inverse current circuit mentioned above is preferably a pair of transistors of complementary form where one is an NPN transistor and the other is a PNP transistor.
Furthermore, in the embodiment of the present invention, the input transistor is structured as a pair of complementary transistors biased to establish a voltage difference of zero volt between the output voltage and the input voltage in the no-load condition. Alternatively, the input transistor is configured by either an NPN transistor or a PNP transistor which is biased in order to have a predetermined positive or negative voltage difference between the output voltage and the input voltage.
Furthermore, in the embodiment of the present invention, a current prevention means is provided to prevent unnecessary current from flowing in the inverse current circuit mentioned above. This current prevention means is structured by a pair of diodes connected to the output transistors and a pair of voltage shift means connected to the inverse current circuit.
According to the present invention, the output circuit is capable of high-speed operation and large output current generation, as well as low power consumption and being used as an output stage of various electronic circuits. Therefore, in a semiconductor test system, for example, the output circuit of the present invention can be advantageously applied to an output stage of the driver circuit for supplying test signals to the semiconductor device under test. The output circuit of the present invention can achieve the goals of high-speed operation, large current output, and low consumption power all at the same time at low cost and compact circuit structure.